The present invention relates to a semiconductor device in which a plurality of semiconductor elements have a SOI (Silicon On Insulator)-Si layer and a method of manufacturing the same. More particularly, the present invention relates to a structure of an element isolation film and a method of manufacturing the same.
In a conventionally-known semiconductor device, a CMOS element and a bipolar element are integrally formed on a SOI substrate (U.S. Pat. No. 5,212,397). The SOI substrate is constituted of a silicon semiconductor substrate (Si-sub) 1 and a buried oxide film (BOX) 2 formed thereon, as shown in FIG. 23. The buried oxide film 2 is formed by doping oxygen ions into the semiconductor substrate. The SOI substrate has a bipolar region 9 and a CMOS region 10. CMOS elements 7 and 8 are formed in the CMOS region 10, whereas a bipolar element is formed in the bipolar region 9. More specifically, the CMOS elements 7 and 8 are formed in a thin single crystalline silicon layer 3 formed on the buried oxide film (BOX) 2 within the CMOS region 10. The buried oxide film (BOX) 2 is deeply etched within the bipolar region 9. Within the etched region of the buried oxide film (BOX) 2, a thick single crystalline silicon layer 4 is formed by epitaxial deposition. A semiconductor element (bipolar element) is formed in the single crystalline layer 4. Although only a single bipolar element is shown in the figure, bipolar elements are separated by an element isolation silicon oxide film 6 formed in the element isolation region. On the other hand, the CMOS elements 7 and 8 are separated by an element isolation silicon oxide film 5 in the element isolation region. The element isolation film 6 of the bipolar region 9 is formed thicker than the element isolation film 5 of the CMOS region 10 and therefore the height of the film 6 from the surface of the substrate is larger than that of the film 5. To explain more specifically, the element isolation film 6 of the bipolar region 9 differs in thickness from the element isolation film 5 of the CMOS region 10, and therefore, their heights from the surface of the substrate differ.
A bipolar transistor has an emitter, base, collector, and collector extraction layer which are formed in the single crystalline silicon layer 4 of the bipolar region 9, and an emitter electrode, base electrode, and a collector electrode which are formed on the single crystalline silicon layer 4. A PMOS transistor of a CMOS transistor structure has a P+ source/drain region formed in the single crystalline silicon layer 3 of the CMOS region, a gate oxide film formed on the single crystalline silicon layer 3, and a gate electrode 7 formed on the gate oxide film. An NMOS transistor of the CMOS transistor structure has an N+ source/drain region formed in the single crystalline silicon layer 3 of the CMOS region, a gate oxide film formed on the single crystalline silicon layer 3, and a gate electrode 8 formed on the gate oxide film.
As described in the above, in the conventional semiconductor device, the element isolation film 6 of the bipolar region 9 is formed thicker than the element isolation film 5 of the CMOS region 10. Thus, the height of the element isolation film 6 from the surface of the substrate is larger than the element isolation film 5. In other words, since the thickness of the element isolation film 6 of the bipolar region differs in thickness from the element isolation film 5 of the CMOS region 10, their heights from the surface of the substrate differ from each other. This makes it difficult to process a wiring layer formed over the bipolar region 9 and the CMOS region 10. More specifically, in the manufacturing process of a semiconductor device having a plurality of SOI-Si layers different in thickness on a single SOI substrate; since element isolation is performed after a plurality of SOI-Si layers different in thickness are formed, the heights of the insulating films of the element isolation region differ. Therefore, it is difficult to process a wiring layer in a wiring formation step performed later. Furthermore, as a result of the insulating films of the element isolation region differing in height, “out-of-focus” occurs in a lithography step later performed, rendering it difficult to perform a micro gate processing.
There is another publication (U.S. Pat. No. 5,294,823) besides the aforementioned publication (U.S. Pat. No. 5,212,397) in which a plurality of single crystalline semiconductor layers different in thickness which are formed on a buried insulating film, are integrally formed into a single chip. However, in this conventional example, the element isolation regions of the bipolar region and the CMOS region 10 differ in height from the surface of a semiconductor substrate. Therefore, the same problems as in U.S. Pat. No. 5,212,397 resides also in U.S. Pat. No. 5,294,823.